The flip-chip bonding is a technology of joining a semiconductor chip to electrodes on a board using solder. The flip-chip bonding is also called C4 bonding. FIG. 1 is a diagram showing the state of a semiconductor chip and a multilayer wiring board after they are flip-chip bonded together according to a conventional technique. The multilayer wiring board is a board having wiring layers and insulating layers that are stacked alternately. The multilayer wiring board is also called a multilayer board or a build-up board. Electrode pads 3 are formed on the surface of an insulating layer 2 being an uppermost layer of a multilayer wiring board 1. Each of the electrode pads 3 is located so as to correspond to an associated one of electrodes of a semiconductor chip 5. The board 1 is covered with a solder resist 6 except at flip-chip bonded joints 4 of the electrode pads 3. At openings of the solder resist 6 on the surfaces of the electrode pads 3, the electrodes of the semiconductor chip 5 and the electrode pads 3 of the board 1 are electrically connected to each other by the flip-chip bonded joints 4 being solder joints. For reinforcing the joining between the semiconductor chip 5 and the board 1, a resin 7 called an underfill is filled between the semiconductor chip 5 and the board 1.
The multilayer wiring board 1 with the semiconductor chip 5 flip-chip bonded thereto is subjected to a temperature cycle test for checking reliability against variation in temperature. In the temperature cycle test, cracks identified by numeral 10 in FIG. 1 are generated in the board 1 at portions adjacent to the electrode pads 3. The cracks 10 occur due to a difference in thermal expansion coefficient between the semiconductor chip 5 and the board 1. The cracks 10 occur particularly at those electrode pads 3 located near an end surface 111 of the semiconductor chip 5. The cracks 10 do not occur in a central direction 12 of the semiconductor chip 5. The reason why the cracks 10 occur at those electrode pads 3 near the end surface 11 of the semiconductor chip 5 is that large stresses are concentrated around the end surface 11 of the semiconductor chip 5 upon cooling in the temperature cycle. These stresses are caused by the difference in thermal expansion coefficient between the semiconductor chip 5 and the multilayer board 1. The cracks 10 having once occurred propagate in the board 1 to thereby cut a wiring layer in the multilayer board 1 beneath the electrode pads 3. As a result, operation failure (disconnection) of a circuit in the multilayer wiring board 1 is induced.
JP-A-H09-102517 discloses a technique for preventing cracks from occurring in solder bumps due to a difference in thermal expansion coefficient between a semiconductor element and a printed board. In this publication, electrodes of the semiconductor element on which the solder bumps are placed each have an elongated oval shape extending in an expansion direction of the semiconductor element. As a result, a joint area of each solder bump in the expansion direction of the semiconductor element is increased to relax concentration of stresses to the root of the solder bump.
This publication, however, discloses the technique for preventing occurrence of the cracks in the solder bumps, and does not disclose a technique for preventing occurrence of the cracks 10 (FIG. 1) in the board 1 at the portions adjacent to the electrode pads 3.